Design based on Coilcraft IC specific transformer B0570-BL. Schematic based on ON Documents:
Since the chosen transformer comes with an auxillary winding anyway, we’re going to use it. Jumpers to switch to DSS may be provided for testing purposes to move to cheaper transformer(s) later on once a transformer vendor is located.
Could use 65kHz since all the application notes do it anyway as well as with the same kind of transformer. The rationale they use is EMI certification starting at 150kHz.
However, the numbers seem somewhat doubtful with it with this transformer, specifically related to the primary inductance being lower than examples. Using 100kHz instead with the hope it will improve margins does not help, since other equations seem to push the convertor into CCM if that is done.
Fsw = 65kHz
Vin = Mains = 230VAC+-15% ~ 310VDC Vinmin = 260VDC Vinmax = 360VDC Vout = 12V Isolated Iout = 1A
Lt = 3.4uH DCR(pri) = 2.570ohm DCR(sec) = 0.038ohm DCR(aux) = 0.285ohm Ll = 95uH N = p:s:a = 1:0.06:0.08 Iout = 1.25A
Rdson = 11ohm Ipeak (max) = 450mA Freq = 65kHz
Vcc OFF = 8.7V Vcc ON = 7.7V Vcc Latch = 4.9V
Assuming 10ms startup time in absence of other constraints.
C >= ICC1 * tstartup / dV
ICC1 = 1.1mA tstartup = 10ms dV = 1.0V (DSS) C >= 11uF
C = 22uF
A smaller value might be acceptable for auxillary winding operation.
Since we’re not using DSS right now, calculations are deferred. AND8125/D may be used for calculations along with eqs. 4-9 on datasheet p.10.
From eq. 10,
(Vnom - Vclamp) / Itrip <= Rlimit <= (Vstby - VCCon)/ICC1
Vnom = 16V (from Vout=12V and naive transformer turns ratio) Vstdby = 9.6V (40% reduction of Vnom per datasheet text) Itrip = 6.3mA (detailed in datasheet text) ICC1 = 1.1mA (spec) Vclamp = 8.7V (spec) VCCon = 8.0V (spec + headroom)
(16V - 8.7V) / 6.3mA <= Rlimit <= (12V - 8V) / 1.1mA 1.16 kohm <= Rlimit <= 3.64 kohm
Turns ratio is:
Nsec / Naux = 0.06 / 0.08 = 0.75
OVP latch activates when clamp current > 6.3mA, or when
Vaux = 8.7V + Rlimit * (6.4mA + 1.1mA)
Vauxl = 17V Voutl = 17V * 0.75 = 12.75V
Vauxl = 35.7V Voutl = 35.7 * 0.75 = 26.78V
Since this is a 12V output, we set overlimit at about 13V.
Rlimit = 1.3K Vauxl = 18.5V Voutl = 13.875V
Note: This calculation does not seem to include the effects of the diode on the auxiliary winding. This diode is most definitely going to shift the calculations.
From datasheet p.15,
Ptot = Pdss + Pmos
Assuming here that Ip = 0.45A and d = 0.65,
Pmos = 1/3 * Ip^2 * d * Rdson = 1/3 * 0.45^2 * 0.65 * 11 = 0.48W
Assuming Pdss < Pmos, we get Ptot < 1W which is the the dissipation capability of the PDIP7 package. For the smaller package, we simply assume it works and don’t bother calculating at this time. We instead hang our hat on the fact that we aren’t planning on using DSS anyway.
Following the datasheet p.16,
N * (Vout + Vf) < Vinmin N * (12V + 0.7V) < 260V N < 20.5 Nactual = 16.67
These calculations don’t match with anything in the datasheet. It seems the output voltage is twice of what a regular flyback convertor equation suggests. Why?
Worst case naive duty cycle,
dcmax = N * Vout / Vinmin = 16.67 * 12.7 / 260 = 0.81
Nominal naive duty cycle,
dctyp = N * Vout / Vin = 16.67 * 12.7 / 310 = 0.68
Duty cycles are extremely borderline. We assume that coilcraft knows what they are doing and this will get resolved due to lower power draw from the secondary that is naively possible. In case this continues to cause trouble, it might be necessary to drop the output voltage down to 10V or so. The transformer should ideally have more turns on secondary than it does.
Vdrainmax = Vin + N(Vout+Vf) + Ip * sqrt(Lf/ Ctot) = 310V + 16.67 * (12.7V) + 0.45A * sqrt (95uH / Ctot) = 521V + 0.45 * sqrt(95uH / Ctot)
This looks fine at first glance against the 700V internal mosfet.
eq.16 and AND8125 eq.1,
Ton = Lp * Ip / Vin = 3.4mH * 0.45A / 310V = 4.95us
eq.17 and AND8125 eq.2,
Toff = Lp * Ip / (N * (Vout + Vf)) = 3.4mH * 0.45A / (16.67 * 12.7V) = 7.227us
eq.18 and AND8125 eq.3,
Tsw = Ton + Toff = 12.177us
Actual Tsw = 1/65kHz = 15.38us
we get Tsw < Actual Tsw, so we should see some dead time and DCM operation.
Note that if we chose 100kHz, we would get
Actual Tsw = 1/100kHz = 10us
with Tsw > Actual Tsw, and what seems like CCM operation. This suggests Lp of the transformer is larger than we would want for 100kHz.
eq.19-21 and AND8125 eq.4-6,
Lpcrit = [(Vin.Vr)^2 . e] / [2 * Fsw * (Pout * ( Vr^2 + 2Vr.Vin + Vin^2]
Vr = N * (Vout + Vf) = 16.67 * 12.7V = 212V
Lpcrit = [(310*212)^2 . e] / [2 * 65*10^3 * Pout * (212^2 + 2*212*310 + 310^2)] = [4.32 × 10^9 . e] / [3.54 × 10^10 * Pout] = 0.12 * e / Pout
For an assumed efficiency of 80% and Pout of 12W, this becomes
Lpcrit = 8mH
If, instead, we had chosen 100kHz,
Lpcrit = [(310*212)^2 . 0.8] / [2 * 100*10^3 * 12 * (212^2 + 2*212*310 + 310^2)] Lpcrit = 5.2mH
As per this equation, our actual Lp is perfectly fine for 12W output at both 65 kHz and 100kHz.
From AND8125, eq.7, eq.8
Vrmax = VinAC * 1.414 - ripple
Using 10% ripple, since that’s what the example does,
Vrmax = 260V - 10% = 234V > 212V
There seems to be enough margin for 10% ripple on input voltage.
eq.22 and AND8125 eq.9,
Lpmax = DCmax * Vinmin * Tsw / Ipmax
DCmax = 45% (design constraint) Vinmin = 260VDC Tsw = 1/Fsw = 15.38us @ 65kHz, 10us @ 100 kHz Ipmax = 450mA
Lpmax = 0.45 * 260V * 15.38us / 450mA = 4mH
Lpmax = 0.45 * 260V * 10us / 450mA = 2.6mH
The 100kHz frequency requires a lower Lp as well. This is in line with the original set of equations, so sticking to 65kHz seems to be reasonable.
Pmax = [Tsw^2 * Vinmin^2 * Vr^2 * e * Fsw] / [2 * Lpmax * Vr^2 + 4 * Lpmax * Vr * Vinmin + 2 * Lpmax * Vinmin^2]
Here, using actual Lp instead of Lpmax, since the transformer is fixed,
Pmax = [(15.38us)^2 * (260V)^2 * (212V)^2 * 0.8 * 65kHz] / [2 * 3.4mH * (212V)^2 + 4 * 3.4mH * 212V * 260V + 2 * 3.4mH * (260V)^2] = 24.67W
Which is somehow way higher than the datasheet suggests. Probably missing something.
We are tentatively targeting 12W - 12.7W of transmitted power.
eq.24, operating duty cycle
d = Ip * Lp / Vin * Tsw = (450mA * 3.4mH) / (310V * 15.38us) = 0.321
This duty cycle is about in line with the DCM and Lp sanity checks, but half that of a generic flyback converter equation.
For worst case,
dmax = 450mA * 3.4mH / (260V * 15.38us) = 0.383
IdRMS = Ip * sqrt(d/3) = 0.45A * sqrt(0.321/3) = 0.147A
Pavg = 1/3 * Ip^2 * d * Rdson = 1/3 * 0.45A^2 * 0.321 * 11ohm = 238mW
The following is the assumption we are making to paper over the likely misunderstood calculations :
The current mode control essentially pushes energy to the primary irrespective of a direct output voltage consideration. The feedback needs to control this push to regulate secondary voltage. When the energy is pushed, it fills up the output capacitor and reaches whatever voltage is needed - probably within some reason. As long as we don’t draw more energy than is being pumped in, the regulation should more or less hold. Once we do, output voltage should drop and output ripple should spike - not because too much energy is being pumped in, which is the regular ripple source, but because the energy is insufficient to keep the capacitor charged.